Hybrid on-line self-test architecture for computational units on embedded processor cores

Safety-critical applications require to reach high fault coverage figures for on-line testing in order to be compliant with currently used functional safety standards. Nowadays, for meeting these constraints different solutions are adopted by semiconductor manufactures. Such approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents several advantages and drawbacks, typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, hardware approaches yield high defect coverage but they are normally invasive and have longer test application time. The aim of this paper is to present a novel Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal is to overcome limitations of both hardware- and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.