Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724644
F. Almeida, P. Bernardi, D. Calabrese, Marco Restifo, M. Reorda, D. Appello, G. Pollaccia, V. Tancorre, R. Ugioli, G. Zoppi
Automotive systems must reach a high reliability in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible defects that could manifest during lifetime. Burn-In (BI) is a manufacturing test phase used for screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing process of complex Systems on Chip (SoCs) mimicking the operational conditions. This paper aims at describing the motivations for and the effectiveness stemming from combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. Moreover, the paper analyses the required tester architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics is used to demonstrate the possible cost reduction.
{"title":"Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test","authors":"F. Almeida, P. Bernardi, D. Calabrese, Marco Restifo, M. Reorda, D. Appello, G. Pollaccia, V. Tancorre, R. Ugioli, G. Zoppi","doi":"10.1109/DDECS.2019.8724644","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724644","url":null,"abstract":"Automotive systems must reach a high reliability in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible defects that could manifest during lifetime. Burn-In (BI) is a manufacturing test phase used for screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing process of complex Systems on Chip (SoCs) mimicking the operational conditions. This paper aims at describing the motivations for and the effectiveness stemming from combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. Moreover, the paper analyses the required tester architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics is used to demonstrate the possible cost reduction.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116664483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724670
Jan Malburg, Karl Janson, J. Raik, F. Dannemann
Current embedded systems are increasingly using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case that parts of the network are damaged, is the key to allow reliable behavior of the system. In this paper, we present an approach for measuring the performance parameters of embedded networks under different load and fault scenarios. First, the performance parameters of the network are measured in the nominal case. This information is then used to create a model of the network. For this model we provide a simulation environment, which injects faults into the network to evaluate the network under failure scenarios. We evaluated our approach on a Network on Chip consisting of 16 nodes arranged in a 4x4 matrix. Our evaluation shows that our approach can evaluate the fault effects in the network with good quality.
{"title":"Fault-Aware Performance Assessment Approach for Embedded Networks","authors":"Jan Malburg, Karl Janson, J. Raik, F. Dannemann","doi":"10.1109/DDECS.2019.8724670","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724670","url":null,"abstract":"Current embedded systems are increasingly using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case that parts of the network are damaged, is the key to allow reliable behavior of the system. In this paper, we present an approach for measuring the performance parameters of embedded networks under different load and fault scenarios. First, the performance parameters of the network are measured in the nominal case. This information is then used to create a model of the network. For this model we provide a simulation environment, which injects faults into the network to evaluate the network under failure scenarios. We evaluated our approach on a Network on Chip consisting of 16 nodes arranged in a 4x4 matrix. Our evaluation shows that our approach can evaluate the fault effects in the network with good quality.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117017749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724642
C. C. Gürsoy, M. Jenihhin, Adeboye Stephen Oyeniran, D. Piumatti, J. Raik, M. Reorda, R. Ubar
The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor.
{"title":"New categories of Safe Faults in a processor-based Embedded System","authors":"C. C. Gürsoy, M. Jenihhin, Adeboye Stephen Oyeniran, D. Piumatti, J. Raik, M. Reorda, R. Ubar","doi":"10.1109/DDECS.2019.8724642","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724642","url":null,"abstract":"The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724645
Ioana Lal, Marius Nicoara, A. Codrean, L. Buşoniu
This paper presents the construction of a new ball balancing robot (ballbot), together with the design of a controller to balance it vertically around a given position in the plane. Requirements on physical size and agility lead to the choice of ball, motors, gears, omnidirectional wheels, and body frame. The electronic hardware architecture is presented in detail, together with timing results showing that real-time control can be achieved. Finally, we design a linear quadratic regulator for balancing, starting from a 2D model of the robot. Experimental balancing results are satisfactory, maintaining the robot in a disc 0.3 m in diameter.
{"title":"Hardware and control design of a ball balancing robot","authors":"Ioana Lal, Marius Nicoara, A. Codrean, L. Buşoniu","doi":"10.1109/DDECS.2019.8724645","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724645","url":null,"abstract":"This paper presents the construction of a new ball balancing robot (ballbot), together with the design of a controller to balance it vertically around a given position in the plane. Requirements on physical size and agility lead to the choice of ball, motors, gears, omnidirectional wheels, and body frame. The electronic hardware architecture is presented in detail, together with timing results showing that real-time control can be achieved. Finally, we design a linear quadratic regulator for balancing, starting from a 2D model of the robot. Experimental balancing results are satisfactory, maintaining the robot in a disc 0.3 m in diameter.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127076084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724637
S. Pointner, Pablo González de Aledo Marugán, R. Wille
Several methods and tools have been proposed which supports designers in verifying embedded systems in early phases of the design process, e.g. at the Electronic System Level (ESL). However, they only show whether an error indeed exists in the system, but it frequently remains open to efficiently locate the source of this error. In this work, we propose a generic error localization methodology. More precisely, by applying code augmentations and conducting further runs of the verification method, it is analyzed what statements may have caused the error. The respectively determined statements then pin-point the verification engineer to possible error locations. By conducing all this on the code level only, the proposed methodology can be applied to any verification method available today. The suitability of the proposed methodology is demonstrated by means of a verification flow based on symbolic execution.
{"title":"Generic Error Localization for the Electronic System Level","authors":"S. Pointner, Pablo González de Aledo Marugán, R. Wille","doi":"10.1109/DDECS.2019.8724637","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724637","url":null,"abstract":"Several methods and tools have been proposed which supports designers in verifying embedded systems in early phases of the design process, e.g. at the Electronic System Level (ESL). However, they only show whether an error indeed exists in the system, but it frequently remains open to efficiently locate the source of this error. In this work, we propose a generic error localization methodology. More precisely, by applying code augmentations and conducting further runs of the verification method, it is analyzed what statements may have caused the error. The respectively determined statements then pin-point the verification engineer to possible error locations. By conducing all this on the code level only, the proposed methodology can be applied to any verification method available today. The suitability of the proposed methodology is demonstrated by means of a verification flow based on symbolic execution.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134324188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724651
K. Petrosyants, M. Kozhukhov, Dmitry Popov
A special RAD-THERM version of TCAD subsystem based on Sentaurus Synopsys platform taking into account different types of irradiation (gamma-rays, neutrons, electrons, protons, single events) and external/internal heating effects was developed and validated to forecast the results of natural experiments, and help the designer on with reliability guarantee. The radiation- and temperature-induced faults were modeled and simulated for Si/SiGe BJTs/HBTs and bulk/SOI MOSFETs as BiCMOS LSI’s components. The causes of device parameter degradation were discussed.
{"title":"Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI’s Components using RAD-THERM TCAD Subsystem","authors":"K. Petrosyants, M. Kozhukhov, Dmitry Popov","doi":"10.1109/DDECS.2019.8724651","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724651","url":null,"abstract":"A special RAD-THERM version of TCAD subsystem based on Sentaurus Synopsys platform taking into account different types of irradiation (gamma-rays, neutrons, electrons, protons, single events) and external/internal heating effects was developed and validated to forecast the results of natural experiments, and help the designer on with reliability guarantee. The radiation- and temperature-induced faults were modeled and simulated for Si/SiGe BJTs/HBTs and bulk/SOI MOSFETs as BiCMOS LSI’s components. The causes of device parameter degradation were discussed.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124984056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724635
M. Skuta, Dominik Macko
A low power or energy efficient hardware operation is nowadays gaining attention. It is especially true for battery-operated or energy-harvesting devices, such as most of the Internet of Things end nodes. For specific applications with rather limited market, the FPGAs are very good alternative. However, evolution of these devices is focused on high-level programming, giving application designers space to focus on application function rather than to be concerned about its low-level implementation on FPGA device – it is handled by automation tools. Thus, new FPGA-application designers are nowadays not very familiar with hardware aspects and it is difficult for them to apply power-reduction techniques in order to create an energy-efficient system. This paper is focused on automation of power-management integration into the FPGA-application design based on abstract specification, which is easy-to-use even for unfamiliar designers. It simplifies and speeds-up the low-power and energy-efficient FPGA-application design process. Moreover, the automation prevents many human-errors and thus it also alleviates the verification process. Experimental results indicate that the proposed power-management scheme is working correctly and it can be automatically generated.
{"title":"Automated Integration of Dynamic Power Management into FPGA-Based Design","authors":"M. Skuta, Dominik Macko","doi":"10.1109/DDECS.2019.8724635","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724635","url":null,"abstract":"A low power or energy efficient hardware operation is nowadays gaining attention. It is especially true for battery-operated or energy-harvesting devices, such as most of the Internet of Things end nodes. For specific applications with rather limited market, the FPGAs are very good alternative. However, evolution of these devices is focused on high-level programming, giving application designers space to focus on application function rather than to be concerned about its low-level implementation on FPGA device – it is handled by automation tools. Thus, new FPGA-application designers are nowadays not very familiar with hardware aspects and it is difficult for them to apply power-reduction techniques in order to create an energy-efficient system. This paper is focused on automation of power-management integration into the FPGA-application design based on abstract specification, which is easy-to-use even for unfamiliar designers. It simplifies and speeds-up the low-power and energy-efficient FPGA-application design process. Moreover, the automation prevents many human-errors and thus it also alleviates the verification process. Experimental results indicate that the proposed power-management scheme is working correctly and it can be automatically generated.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127109208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724672
S. Carlo, J. E. R. Condia, M. Reorda
GPGPUs have been increasingly successful in the past years in many application domains, due to their high parallel processing capabilities and energy performance. More recently, they started to be used in areas (such as automotive) where safety is also an important parameter. However, their architectural complexity and advanced technology level create challenges when matching the required reliability targets. This requires devising solutions to perform in-field test, thus allowing the systematic detection of possible permanent faults. These faults are caused by aging or external factors that affect the application execution and potentially generate critical misbehaviors. Moreover, effective in-field test techniques oriented to verify the integrity of GPGPU modules during in-field operation are still missed. In this work, we propose a method to generate self-test procedures able to detect all static faults affecting the scheduler memory existing in each streaming multiprocessor (SM) of a GPGPU. NVIDIA CUDA-C is selected as high-level programing language. The experimental results are obtained employing the NVIDIA Nsight Debugger on a NVIDIA-GEFORCE GTX GPU and a memory fault simulator.
{"title":"On the in-field test of the GPGPU scheduler memory","authors":"S. Carlo, J. E. R. Condia, M. Reorda","doi":"10.1109/DDECS.2019.8724672","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724672","url":null,"abstract":"GPGPUs have been increasingly successful in the past years in many application domains, due to their high parallel processing capabilities and energy performance. More recently, they started to be used in areas (such as automotive) where safety is also an important parameter. However, their architectural complexity and advanced technology level create challenges when matching the required reliability targets. This requires devising solutions to perform in-field test, thus allowing the systematic detection of possible permanent faults. These faults are caused by aging or external factors that affect the application execution and potentially generate critical misbehaviors. Moreover, effective in-field test techniques oriented to verify the integrity of GPGPU modules during in-field operation are still missed. In this work, we propose a method to generate self-test procedures able to detect all static faults affecting the scheduler memory existing in each streaming multiprocessor (SM) of a GPGPU. NVIDIA CUDA-C is selected as high-level programing language. The experimental results are obtained employing the NVIDIA Nsight Debugger on a NVIDIA-GEFORCE GTX GPU and a memory fault simulator.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123997097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724661
O. Novák
It was found that the linear binary codes can be extended by a relatively high number of nonlinear check bits in such a way that the code words preserve the value of the maximum number of independently specified bits from the original linear code words. These extended nonlinear binary codes can be used for pattern compression and decompression. The number of scan chains loaded in parallel from the sequential decompressor may be increased while the number of specified bits is kept. The nonlinear structures guarantee the number of independently specified bits within the whole decompressed test pattern independently on the scan chain clock cycle for a substantially higher number of parallel scan chains than the linear decompressors while the number of bits transferred from the tester is kept. We proposed an algorithm that finds the appropriate nonlinear modification circuit of the sequential decompressor and verifies the test pattern quality for different numbers of care bits in a test pattern.
{"title":"Nonlinear Compression Codes Used In IC Testing","authors":"O. Novák","doi":"10.1109/DDECS.2019.8724661","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724661","url":null,"abstract":"It was found that the linear binary codes can be extended by a relatively high number of nonlinear check bits in such a way that the code words preserve the value of the maximum number of independently specified bits from the original linear code words. These extended nonlinear binary codes can be used for pattern compression and decompression. The number of scan chains loaded in parallel from the sequential decompressor may be increased while the number of specified bits is kept. The nonlinear structures guarantee the number of independently specified bits within the whole decompressed test pattern independently on the scan chain clock cycle for a substantially higher number of parallel scan chains than the linear decompressors while the number of bits transferred from the tester is kept. We proposed an algorithm that finds the appropriate nonlinear modification circuit of the sequential decompressor and verifies the test pattern quality for different numbers of care bits in a test pattern.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125876721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724649
Amin Malekpour, R. Ragel, Daniel Murphy, A. Ignjatović, S. Parameswaran
We present a Hardware Trojan (HT) detection, identification and recovery mechanism for Multiprocessor Systems on Chips (MPSoCs). Our method utilizes on-line testing to mitigate the effects of hardware Trojans in a computing system using a Hardware Security Monitor (HSM), a trusted hardware module, and an On-line Test Procedure (OTP), a software module. The proposed approach focuses on mitigating hardware Trojans with a permanent impact on the computing system and enables MPSoCs to continue functioning in the presence of the hardware Trojans. We have successfully validated the proposed method by implementing known hardware Trojans from Trust-Hub on a Xilinx ML605 FPGA. The implementation incurred 4.5% area and 9.1% execution time overheads for a set of benchmark applications. Compared to the state of the art, the proposed mechanism’s area and power overheads are significantly lower while the execution time overhead is slightly higher. State of the art systems utilizing differing cores have been shown to be effective in simulation environments, while the proposed mechanism has been implemented in FPGAs to illustrate that such a system can be realized in hardware.
{"title":"Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing","authors":"Amin Malekpour, R. Ragel, Daniel Murphy, A. Ignjatović, S. Parameswaran","doi":"10.1109/DDECS.2019.8724649","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724649","url":null,"abstract":"We present a Hardware Trojan (HT) detection, identification and recovery mechanism for Multiprocessor Systems on Chips (MPSoCs). Our method utilizes on-line testing to mitigate the effects of hardware Trojans in a computing system using a Hardware Security Monitor (HSM), a trusted hardware module, and an On-line Test Procedure (OTP), a software module. The proposed approach focuses on mitigating hardware Trojans with a permanent impact on the computing system and enables MPSoCs to continue functioning in the presence of the hardware Trojans. We have successfully validated the proposed method by implementing known hardware Trojans from Trust-Hub on a Xilinx ML605 FPGA. The implementation incurred 4.5% area and 9.1% execution time overheads for a set of benchmark applications. Compared to the state of the art, the proposed mechanism’s area and power overheads are significantly lower while the execution time overhead is slightly higher. State of the art systems utilizing differing cores have been shown to be effective in simulation environments, while the proposed mechanism has been implemented in FPGAs to illustrate that such a system can be realized in hardware.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127745827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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