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引用次数: 5
摘要
在0.8 um CMOS上设计了一个高速除以2的预分频器。提出了一种具有源折叠二极管箝位的新型类ecl D触发器。采用适当晶体管尺寸比的源折叠二极管可以获得显著的速度提升，通过设计低功耗D触发器并去除额外的输入放大缓冲器可以降低功耗。该预分频器的模拟最大输入频率在5ma时可达3.15 GHz，在3.3 V时1.6 mA时可达1.8 GHz。
A high-speed divide-by-2 prescaler is designed in a 0.8 um CMOS. New ECL-like D flip-flop is proposed having source-folded diode clamping. Significant amount of speed up can be obtained using source-folded diode with proper sizing ratio of transistors, and lower power consumption can be obtained by designing low power D flip-flop and removing additional input-amplifying buffer. The simulated maximum input frequency of the suggested prescaler reaches up to 3.15 GHz with only 5 mA and 1.8 GHz with 1.6 mA at 3.3 V.
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