基于级联半桥的多电平直流链路逆变器拓扑的最近电平控制方案

R. Sakile, A. Bhanuchandar, Kasoju Bharath Kumar, D. Vamshy, Bandela Supriya, Kowstubha Palle
{"title":"基于级联半桥的多电平直流链路逆变器拓扑的最近电平控制方案","authors":"R. Sakile, A. Bhanuchandar, Kasoju Bharath Kumar, D. Vamshy, Bandela Supriya, Kowstubha Palle","doi":"10.1109/SPIN52536.2021.9566056","DOIUrl":null,"url":null,"abstract":"In this paper, a Nearest Level Control (NLC) scheme for Reduced Switch Count (RSC) cascaded half-bridge based Multilevel DC-Link (MLDCL)inverter topology with three different source configurations (1:1:1:1, 1:2:3:4 and 1:2:4:8) have been explained clearly. For generating particular level in the inverter output, NLC technique has been utilized. The NLC technique is generally a low switching frequency technique thereby switching losses are greatly reduces and it is suitable for any kind of inverter topology. The MLDCL topology consists of 8 unidirectional switches in the level generator side, 4 unidirectional switches in the polarity generator side and 4 dc sources. For generating P-level output, only P+3 switches are required then the requirement of gate driver circuits, protection circuits have been reduced. Basically, NLC technique is more suitable for higher level inverter topologies and provides best harmonic performance as compared with conventional Pulse Width Modulation (PWM) techniques. The operation and feasibility of the topology with control scheme have been validated through the MATLAB/Simulink platform.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Nearest Level Control Scheme for Reduced Switch Count Cascaded Half-Bridge Based Multilevel DC Link Inverter Topology\",\"authors\":\"R. Sakile, A. Bhanuchandar, Kasoju Bharath Kumar, D. Vamshy, Bandela Supriya, Kowstubha Palle\",\"doi\":\"10.1109/SPIN52536.2021.9566056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a Nearest Level Control (NLC) scheme for Reduced Switch Count (RSC) cascaded half-bridge based Multilevel DC-Link (MLDCL)inverter topology with three different source configurations (1:1:1:1, 1:2:3:4 and 1:2:4:8) have been explained clearly. For generating particular level in the inverter output, NLC technique has been utilized. The NLC technique is generally a low switching frequency technique thereby switching losses are greatly reduces and it is suitable for any kind of inverter topology. The MLDCL topology consists of 8 unidirectional switches in the level generator side, 4 unidirectional switches in the polarity generator side and 4 dc sources. For generating P-level output, only P+3 switches are required then the requirement of gate driver circuits, protection circuits have been reduced. Basically, NLC technique is more suitable for higher level inverter topologies and provides best harmonic performance as compared with conventional Pulse Width Modulation (PWM) techniques. The operation and feasibility of the topology with control scheme have been validated through the MATLAB/Simulink platform.\",\"PeriodicalId\":343177,\"journal\":{\"name\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN52536.2021.9566056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN52536.2021.9566056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

本文对三种不同源配置(1:1:1:1:1,1:2:3:4和1:2:4:8)的基于级联半桥的减少开关计数(RSC)多电平DC-Link (MLDCL)逆变器拓扑结构的最近电平控制(NLC)方案进行了清晰的解释。为了在逆变器输出中产生特定电平,采用了NLC技术。NLC技术通常是一种低开关频率技术,从而大大降低了开关损耗,适用于任何类型的逆变器拓扑。MLDCL拓扑由电平发生器侧的8个单向开关、极性发生器侧的4个单向开关和4个直流电源组成。产生P级输出只需要P+3个开关,减少了对栅极驱动电路、保护电路的要求。基本上,与传统的脉宽调制(PWM)技术相比,NLC技术更适合于更高电平的逆变器拓扑,并提供最佳的谐波性能。通过MATLAB/Simulink平台验证了拓扑控制方案的可操作性和可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A Nearest Level Control Scheme for Reduced Switch Count Cascaded Half-Bridge Based Multilevel DC Link Inverter Topology
In this paper, a Nearest Level Control (NLC) scheme for Reduced Switch Count (RSC) cascaded half-bridge based Multilevel DC-Link (MLDCL)inverter topology with three different source configurations (1:1:1:1, 1:2:3:4 and 1:2:4:8) have been explained clearly. For generating particular level in the inverter output, NLC technique has been utilized. The NLC technique is generally a low switching frequency technique thereby switching losses are greatly reduces and it is suitable for any kind of inverter topology. The MLDCL topology consists of 8 unidirectional switches in the level generator side, 4 unidirectional switches in the polarity generator side and 4 dc sources. For generating P-level output, only P+3 switches are required then the requirement of gate driver circuits, protection circuits have been reduced. Basically, NLC technique is more suitable for higher level inverter topologies and provides best harmonic performance as compared with conventional Pulse Width Modulation (PWM) techniques. The operation and feasibility of the topology with control scheme have been validated through the MATLAB/Simulink platform.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Temperature Compensation Circuit for ISFET based pH Sensor Knowledge Adaptation for Cross-Domain Opinion Mining Voltage Profile Enhancement of a 33 Bus System Integrated with Renewable Energy Sources and Electric Vehicle Power Quality Enhancement of Cascaded H Bridge 5 Level and 7 Level Inverters PIC simulation study of Beam Tunnel for W- Band high power Gyrotron
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1