Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren
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引用次数: 1
摘要
在标准65nm CMOS中模拟了一个4 mw 8 b 600 ms /s 2 b/ cycle (2 b/C)逐次逼近寄存器(SAR)模数转换器(ADC)。通过采用基准电容式DAC、四输入比较器和数据校准单元，可以实现更高的速度。在采样率为600 MS/s的情况下，该ADC的峰值信噪比为52.7 dB，在输入频率为302 mhz的情况下，ENOB保持在7.5位以上。该ADC的FoM为34.5 fJ/转换步长，采样率为600 ms /s，电源为1.2 v。
A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC
A 4-mW 8-b 600-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is simulated in a standard 65-nm CMOS. By adopting reference capacitive DAC, four-input comparator and the data calibration unit, the proposed ADC could achieve higher speed. As simulated at sampling rate of 600 MS/s, the proposed ADC could achieve a peak SNR of 52.7 dB and maintain ENOB higher than 7.5 bits up to 302-MHz input signal frequency. The FoM of proposed ADC is 34.5 fJ/conversion-step at a 600-MS/s sampling rate and a 1.2-V supply.
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