新型垂直柱型晶体管4F2 DRAM单元

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2011-10-13 DOI:10.1109/ESSDERC.2011.6044197

Hyun-Woo Chung, Huijung Kim, Hyungi Kim, Kanguk Kim, Sua Kim, Ki-Whan Song, Jiyoung Kim, Y. Oh, Y. Hwang, H. Hong, G. Jin, C. Chung

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引用次数: 27

摘要

采用30nm制程技术，成功开发出用于未来DRAM器件的新型VPT 4F2单元结构。VPT具有33μA的优良电流驱动能力和77mV/dec的陡亚阈值斜率。该VPT装置在静态模式下表现出良好的固位特性。采用渐进式结型可以降低浮体效应，即使在柱型通道中也是如此。此外，与传统的8F2和6F2电池相比，VPT每片晶圆的总晶片产量高出约60%和30%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.

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2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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