{"title":"12纳米FinFET技术的蓝牙低能量发射器的开源可完全合成ADPLL","authors":"Kyumin Kwon, Omar Abdelatty, D. Wentzloff","doi":"10.1109/RFIC54546.2022.9863190","DOIUrl":null,"url":null,"abstract":"In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology\",\"authors\":\"Kyumin Kwon, Omar Abdelatty, D. Wentzloff\",\"doi\":\"10.1109/RFIC54546.2022.9863190\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.\",\"PeriodicalId\":415294,\"journal\":{\"name\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC54546.2022.9863190\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology
In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.