特定于ATM应用程序的集成处理器

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606663

A. Harasawa, T. Kaganoi, T. Kanoh, H. Nishizaki, M. Suzuki, H. Tomizawa, T. Shindou

{"title":"特定于ATM应用程序的集成处理器","authors":"A. Harasawa, T. Kaganoi, T. Kanoh, H. Nishizaki, M. Suzuki, H. Tomizawa, T. Shindou","doi":"10.1109/CICC.1997.606663","DOIUrl":null,"url":null,"abstract":"An application specific integrated processor designed for ATM cell processing applications is described in this paper. A new dedicated architecture consisting of a custom-made CPU core, a pipeline input cell buffer and a content addressable memory (CAM) is employed to realize both high performance data processing and functional re-configurability. The chip has been implemented on 0.5 /spl mu/m CMOS. It consumes 2400 mW power under 3.3 V supply at 52 MHz clock frequency for a 155 Mbps high speed cell data stream. Programs for several different applications have been developed and are running on this chip. As a result of evaluation, each application program satisfies a required performance.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"An ATM application specific integrated processor\",\"authors\":\"A. Harasawa, T. Kaganoi, T. Kanoh, H. Nishizaki, M. Suzuki, H. Tomizawa, T. Shindou\",\"doi\":\"10.1109/CICC.1997.606663\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An application specific integrated processor designed for ATM cell processing applications is described in this paper. A new dedicated architecture consisting of a custom-made CPU core, a pipeline input cell buffer and a content addressable memory (CAM) is employed to realize both high performance data processing and functional re-configurability. The chip has been implemented on 0.5 /spl mu/m CMOS. It consumes 2400 mW power under 3.3 V supply at 52 MHz clock frequency for a 155 Mbps high speed cell data stream. Programs for several different applications have been developed and are running on this chip. As a result of evaluation, each application program satisfies a required performance.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文介绍了一种针对ATM小区处理应用而设计的专用集成处理器。采用了一种新的专用架构，由一个定制的CPU核心、一个管道输入单元缓冲区和一个内容可寻址存储器(CAM)组成，实现了高性能的数据处理和功能可重构性。该芯片已在0.5 /spl μ m CMOS上实现。它在3.3 V电源下消耗2400兆瓦功率，52 MHz时钟频率为155 Mbps高速蜂窝数据流。几个不同的应用程序已经开发出来，并在这个芯片上运行。作为评估的结果，每个应用程序都满足要求的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

An ATM application specific integrated processor

An application specific integrated processor designed for ATM cell processing applications is described in this paper. A new dedicated architecture consisting of a custom-made CPU core, a pipeline input cell buffer and a content addressable memory (CAM) is employed to realize both high performance data processing and functional re-configurability. The chip has been implemented on 0.5 /spl mu/m CMOS. It consumes 2400 mW power under 3.3 V supply at 52 MHz clock frequency for a 155 Mbps high speed cell data stream. Programs for several different applications have been developed and are running on this chip. As a result of evaluation, each application program satisfies a required performance.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of CICC 97 - Custom Integrated Circuits Conference

自引率

0.00%

发文量

期刊最新文献

DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1 Self-calibration of digital phase-locked loops Multi-layer over-the-cell routing with obstacles A 2.4 V, 700 /spl mu/W, 0.18 mm/sup 2/ second-order demodulator for high-resolution /spl Sigma//spl Delta/ DACs A single-chip controller for 1.2 Gbps shared buffer ATM switches