Scalable hardware implementation for Quasi-Dyadic Goppa encoder

Error correcting codes are useful tools not only for increasing channel reliability in telecommunications systems, but also for the asymmetric encryption cryptographic schemes. Their operation consists basically in encoding messages into codewords for transmission; once received, these messages are decoded and the original message is recovered after the removal of all bit errors introduced either due to interferences in the medium or intentionally during the encryption process. Both encoding and decoding operations can be implemented as software libraries and/or hardware circuits, although the latter is sometimes preferable due to the higher throughput they provide. One particular type of error correcting code has particular interest in the field of cryptography: binary Quasi-Dyadic Goppa (QD-Goppa) codes, a subset of binary Goppa codes. Indeed, these codes were proposed as a replacement for generic binary Goppa codes in cryptographic applications, since their internal structure allows the optimization of execution time and storage requirements for public and private keys. Despite the interest of such codes, to the best of our knowledge the literature does not include hardware implementation and evaluation of such codes. Aiming to close this gap, in this paper we discuss our results when designing and simulating a scalable hardware architecture for the encoding operation of binary QD-Goppa codes. This architecture was described using VHDL and simulated in Synopsys tools for security levels of 80 to 256 bits, using a 90nm cell library. With this architecture, we obtained processing times from 95 ms to 12 μs and an area occupation from 850 GE to 42 kGE, which allow its utilization even in restricted-resource applications.