S. Z. Ahmed, Yuhui Bai, Imen Dhif, Laurent Lambert, Imen Mhedhbi, P. Garda, B. Granado, K. Hachicha, A. Pinna, Fakhreddine Ghaffari, A. Histace, O. Romain
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In this paper we present an hardware realisation for an image coder used in the SmartEEG project. This collaborative project has the aim of the conception of a multimodal tool for EEG signal to allow transmission of a complete examination of a patient. We show that we can expect good performance on a FPGA board for the time consuming part of this tool that is the image coder.
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