Buffered interconnects in 3D IC layout design

A very important challenge in designing through-silicon via (TSV)-based 3D ICs is to accurately estimate, through all stages of the physical design, the interconnect delay which is strongly dependent on the layout of 3D IC. The earlier in the design process and more accurate it can be done; the better design decisions can be made. Incorporating an optimal buffer insertion approach in the early layout design stage can significantly minimize delay and power in 3D circuits. Unlike 2D ICs, buffer insertion in 3D ICs needs careful consideration of additional design constraints in interconnects spanning multiple device layers. In this paper, we propose a novel buffer insertion scheme for delay optimization during 3D floorplanning. For individual 3D nets, the algorithm efficiently computes the desired distance between consecutive buffers (buffer insertion length), which depends on the non-negligible TSV RC delay contribution of the net. This technique of variable buffer insertion length, used during floorplanning, allows optimizing buffers for individual 3D interconnects and reduces overall buffer count by up to 25% and total power consumption by up to 12%. The proposed approach also includes a method for buffer insertion around a TSV, based on the TSV location and its RC delay. Our experiments suggest that the proposed method of buffer planning around TSVs avoids delay violation and reduces delay across TSVs up to 11%, minimizing buffer usage. The paper also analyzes the impact of key parameters such as buffer size and TSV contact resistance on the delay and power dissipation in 3D interconnects.