一个低功耗和紧凑的桌面ATM PMD

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606641

Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii

{"title":"一个低功耗和紧凑的桌面ATM PMD","authors":"Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii","doi":"10.1109/CICC.1997.606641","DOIUrl":null,"url":null,"abstract":"A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 /spl mu/m CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm/sup 2/ are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low power and compact desktop ATM PMD\",\"authors\":\"Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii\",\"doi\":\"10.1109/CICC.1997.606641\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 /spl mu/m CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm/sup 2/ are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606641\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

在0.35 /spl mu/m的CMOS工艺下，开发了一种用于25.6 Mb/s ATM接口的PMD子层电路。虽然它包含一个UTP 100m电缆均衡器电路和一个时钟恢复电路，但实现了低功率74 mW和小芯片面积2.52 mm/sup 2/。利用该电路，实现了一个六端口25.6 Mb/s的ATM接口芯片。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low power and compact desktop ATM PMD

A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 /spl mu/m CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm/sup 2/ are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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