A synthesis method for mixed synchronous/asynchronous behavior

We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms/spl minus/edge-triggered and level-sensitive/spl minus/for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.<>