High-resolution Time-domain Reflectometry Analysis in Back-end-of-line (BEOL) by Recursive Circuit Modelling

In the prevailing era of Internet of Things (IoT), the conventional failure analysis methodologies are more and more challenged by largely increased I/O density and data throughput with complex chip structures developed such as 3D IC and 2.5D packaging technology. Recently, impulse-based time-domain reflectometry (TDR) has gradually become a popular method to quickly localize a failure point in 2.5D/3D chip package with high resolution. However, it is still a big challenge to apply such TDR analysis for the defect characterization inside the die. In this work, a recursive modeling technique is proposed to enable the TDR analysis inside the die to the frontend-of-line (FEOL) interface.