Design centric modeling of digital hardware

Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable overhead can be needed to code well-known hardware patterns such as FSMs. Finally, the simulation algorithm prevents efficient simulation (e.g. two-state or cycle-based simulation) as well as advanced model analysis (e.g. X-propagation) or fosters an execution that is not in sync with the language definition. Therefore, we developed a design centric modeling approach that allows a clear specification of the design intent and provides freedom for various target HDLs and modeling styles. Since our approach is specified without underlying simulation semantics, we provide a formal definition considering only certain points in simulation traces, thus enabling various ways for simulation. To avoid syntactic sugar, we selected a metamodeling based approach, which we use as part of a modeldriven generation-focused design approach.