Pub Date : 2016-10-07DOI: 10.1109/HLDVT.2016.7748252
L. Besnard, T. Gautier, Clément Guy, P. Guernic, J. Talpin, Brian R. Larson, Etienne Borde
In system design, an architecture specification or model serves, among other purposes, as a repository to share knowledge about the system being designed. Such a repository enables automatic generation of analytical models for different aspects relevant to system design (timing, reliability, security, etc.). The Architecture Analysis and Design Language (AADL) is a standard proposed by SAE to express architecture specifications and share knowledge between the different stakeholders about the system being designed. To support unambiguous reasoning, formal verification, high-fidelity simulation of architecture specifications in a modelbased AADL design workflow, we have defined a formal semantics for the behavior specification of the AADL, the presentation of this semantics is the aim of this paper.
{"title":"Formal semantics of behavior specifications in the architecture analysis and design language standard","authors":"L. Besnard, T. Gautier, Clément Guy, P. Guernic, J. Talpin, Brian R. Larson, Etienne Borde","doi":"10.1109/HLDVT.2016.7748252","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748252","url":null,"abstract":"In system design, an architecture specification or model serves, among other purposes, as a repository to share knowledge about the system being designed. Such a repository enables automatic generation of analytical models for different aspects relevant to system design (timing, reliability, security, etc.). The Architecture Analysis and Design Language (AADL) is a standard proposed by SAE to express architecture specifications and share knowledge between the different stakeholders about the system being designed. To support unambiguous reasoning, formal verification, high-fidelity simulation of architecture specifications in a modelbased AADL design workflow, we have defined a formal semantics for the behavior specification of the AADL, the presentation of this semantics is the aim of this paper.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114566284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748270
Rosario Distefano, N. Goncharenko, F. Fummi, R. Giugno, Gary D Bader, N. Bombieri
Qualitative modelling in systems biology is increasingly adopted as it allows predicting important properties of biological systems even when quantitative information of such systems are unknown. Even though different tools for qualitative modelling have been recently proposed, their lack of automatism and their unstructured simulation core limit their applicability to non-complex biological networks. This paper presents SyQUAL, a platform for qualitative modelling and simulation of biological systems. It consists of two main layers: a Web-based framework that allows users to (i) import models described in the standard Systems Biology Markup Language (SBML), (ii) easily define properties to observe, and (iii) run simulations by hiding the underlying layer, that is, a SystemC-based core simulator that allows simulating the systems through a discrete event-based model of computation at different levels of details. The paper shows how SyQUAL has been applied to identify the attractors and to analyse the system robustness/sensitivity under perturbations of the Colitis-associated Colon Cancer (CAC) network.
{"title":"SyQUAL: a platform for qualitative modelling and simulation of biological systems","authors":"Rosario Distefano, N. Goncharenko, F. Fummi, R. Giugno, Gary D Bader, N. Bombieri","doi":"10.1109/HLDVT.2016.7748270","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748270","url":null,"abstract":"Qualitative modelling in systems biology is increasingly adopted as it allows predicting important properties of biological systems even when quantitative information of such systems are unknown. Even though different tools for qualitative modelling have been recently proposed, their lack of automatism and their unstructured simulation core limit their applicability to non-complex biological networks. This paper presents SyQUAL, a platform for qualitative modelling and simulation of biological systems. It consists of two main layers: a Web-based framework that allows users to (i) import models described in the standard Systems Biology Markup Language (SBML), (ii) easily define properties to observe, and (iii) run simulations by hiding the underlying layer, that is, a SystemC-based core simulator that allows simulating the systems through a discrete event-based model of computation at different levels of details. The paper shows how SyQUAL has been applied to identify the attractors and to analyse the system robustness/sensitivity under perturbations of the Colitis-associated Colon Cancer (CAC) network.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748266
Sarmad Tanwir, M. Hsiao, L. Lingappan
Iterative scan diagnosis is often needed for both the first silicon and the hard-to-diagnose chips. The chips in question are extracted from wafers and re-tested on a debug platform to arrive at a reasonable number of probable defect candidates that can be physically analyzed. This requires a large setup time and multiple iterations of deterministic diagnostic test pattern generation and application. In every iteration, offline software tools are used to diagnose observed failures and generate the needed new patterns to prune the list of defect candidates. In this paper, we propose an online approach for generating additional diagnostic patterns for the hard-to-diagnose chips without moving them to the debug platform. We generate these patterns directly on the tester through a fault model independent hardware-in-the-loop evolutionary algorithm. This algorithm is guided by a lightweight fitness metric that is solely based on the mismatches observed by applying the newly generated patterns to a pair of circuits consisting of a known good die and the chip being diagnosed. We evaluated our technique by comparing our results against a state-of-the-art commercial diagnostic pattern generation tool. Using our generated patterns, we were able to match the diagnosis quality of the commercial tool, while incurring significantly less runtime than the commercial tool on average. Our technique also eliminates the setup and other overhead costs of offline iterative diagnosis, which amounts to additional time savings.
{"title":"Hardware-in-the-loop model-less diagnostic test generation","authors":"Sarmad Tanwir, M. Hsiao, L. Lingappan","doi":"10.1109/HLDVT.2016.7748266","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748266","url":null,"abstract":"Iterative scan diagnosis is often needed for both the first silicon and the hard-to-diagnose chips. The chips in question are extracted from wafers and re-tested on a debug platform to arrive at a reasonable number of probable defect candidates that can be physically analyzed. This requires a large setup time and multiple iterations of deterministic diagnostic test pattern generation and application. In every iteration, offline software tools are used to diagnose observed failures and generate the needed new patterns to prune the list of defect candidates. In this paper, we propose an online approach for generating additional diagnostic patterns for the hard-to-diagnose chips without moving them to the debug platform. We generate these patterns directly on the tester through a fault model independent hardware-in-the-loop evolutionary algorithm. This algorithm is guided by a lightweight fitness metric that is solely based on the mismatches observed by applying the newly generated patterns to a pair of circuits consisting of a known good die and the chip being diagnosed. We evaluated our technique by comparing our results against a state-of-the-art commercial diagnostic pattern generation tool. Using our generated patterns, we were able to match the diagnosis quality of the commercial tool, while incurring significantly less runtime than the commercial tool on average. Our technique also eliminates the setup and other overhead costs of offline iterative diagnosis, which amounts to additional time savings.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121649961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748251
K. S. Luckow, C. Pasareanu
We present LOG2MODEL, an approach, supported by a tool, that builds behavioral models from log data. The logged data consists of time series encoding the values of the states of a system observed at discrete time steps. The models generated are Discrete-Time Markov Chains with states and transitions representing the values recorded in the log. The models contain key information that can be visualized and analyzed with respect to safety, delays, throughput etc, using off-the-shelf model checkers such as PRISM. The analysis results can be further used by users or automated tools to monitor and alter the system behavior. We present the architecture of LOG2MODEL and its application in the context of autonomous operations in the airspace domain.
{"title":"Log2model: inferring behavioral models from log data","authors":"K. S. Luckow, C. Pasareanu","doi":"10.1109/HLDVT.2016.7748251","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748251","url":null,"abstract":"We present LOG2MODEL, an approach, supported by a tool, that builds behavioral models from log data. The logged data consists of time series encoding the values of the states of a system observed at discrete time steps. The models generated are Discrete-Time Markov Chains with states and transitions representing the values recorded in the log. The models contain key information that can be visualized and analyzed with respect to safety, delays, throughput etc, using off-the-shelf model checkers such as PRISM. The analysis results can be further used by users or automated tools to monitor and alter the system behavior. We present the architecture of LOG2MODEL and its application in the context of autonomous operations in the airspace domain.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122859947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748269
Subarna Sinha, D. Dill
Boolean implications (if-then rules) provide a conceptually simple, uniform and highly scalable way to find associations between pairs of random variables. In this paper, we describe how Boolean implications can be derived from large, heterogeneous cancer data sets. We demonstrate two applications of Boolean implications to discover new actionable insights in cancer biology.
{"title":"Deciphering cancer biology using boolean methods","authors":"Subarna Sinha, D. Dill","doi":"10.1109/HLDVT.2016.7748269","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748269","url":null,"abstract":"Boolean implications (if-then rules) provide a conceptually simple, uniform and highly scalable way to find associations between pairs of random variables. In this paper, we describe how Boolean implications can be derived from large, heterogeneous cancer data sets. We demonstrate two applications of Boolean implications to discover new actionable insights in cancer biology.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127826802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748259
Daniel Yunge, Sangyoung Park, Philipp H. Kindt, G. Pravadelli, S. Chakraborty
In the Internet of Things (IoT), our surrounding will include a large variety of devices from different manufacturers. One of its promising branches, the medical IoT, will also be accompanied by heterogeneous smart-home infrastructures. However, the efficacy of a medical IoT application will depend on how well the surrounding smart devices collaborate with it to serve the individual needs of the users. Pre-programmed solutions lack flexibility to adapt to each need and environment, and fail to make full use of the capabilities of a set of smart devices. In this paper, we propose a concept based on the flexible and user-friendly synthesis and switching of services for medical IoT applications. The crux of the concept is to provide a methodology in which non-experts can dynamically define services based on their needs. We describe a potential scenario, discuss the associated challenges, and present preliminary results on the feasibility of this approach. Particularly, we focus on design aspects for realizing the concept and propose the use of interpreters on the smart devices as alternative solution. We show that such an approach is feasible in terms of implementation and energy consumption while still maintaining the full flexibility of the service synthesis.
{"title":"Dynamic service synthesis and switching for medical IoT and ambient assisted living","authors":"Daniel Yunge, Sangyoung Park, Philipp H. Kindt, G. Pravadelli, S. Chakraborty","doi":"10.1109/HLDVT.2016.7748259","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748259","url":null,"abstract":"In the Internet of Things (IoT), our surrounding will include a large variety of devices from different manufacturers. One of its promising branches, the medical IoT, will also be accompanied by heterogeneous smart-home infrastructures. However, the efficacy of a medical IoT application will depend on how well the surrounding smart devices collaborate with it to serve the individual needs of the users. Pre-programmed solutions lack flexibility to adapt to each need and environment, and fail to make full use of the capabilities of a set of smart devices. In this paper, we propose a concept based on the flexible and user-friendly synthesis and switching of services for medical IoT applications. The crux of the concept is to provide a methodology in which non-experts can dynamically define services based on their needs. We describe a potential scenario, discuss the associated challenges, and present preliminary results on the feasibility of this approach. Particularly, we focus on design aspects for realizing the concept and propose the use of interpreters on the smart devices as alternative solution. We show that such an approach is feasible in terms of implementation and energy consumption while still maintaining the full flexibility of the service synthesis.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130370934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748262
Guantao Liu, T. Schmidt, R. Dömer
The SystemC IEEE standard is widely used for system design. While the sequential reference simulator is based on Discrete Event Simulation (DES), Parallel DES (PDES) approaches have been proposed for multi-core platforms. This paper proposes a dynamic load-profiling and segment-aware scheduling algorithm with optimized thread dispatching to maximize parallel SystemC simulation speed, which generally can be applied to all work-sharing PDES approaches. Based on a compile-time generated Segment Graph (SG), our scheduler can accurately predict the run time of the thread segments ahead and thus make better dispatching decisions. In the systematic evaluation, our segment-aware scheduler consistently shows a significant performance gain on top of the order-of-magnitude speedup of PDES, when compared with the previous scheduling policies.
{"title":"A segment-aware multi-core scheduler for system C PDES","authors":"Guantao Liu, T. Schmidt, R. Dömer","doi":"10.1109/HLDVT.2016.7748262","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748262","url":null,"abstract":"The SystemC IEEE standard is widely used for system design. While the sequential reference simulator is based on Discrete Event Simulation (DES), Parallel DES (PDES) approaches have been proposed for multi-core platforms. This paper proposes a dynamic load-profiling and segment-aware scheduling algorithm with optimized thread dispatching to maximize parallel SystemC simulation speed, which generally can be applied to all work-sharing PDES approaches. Based on a compile-time generated Segment Graph (SG), our scheduler can accurately predict the run time of the thread segments ahead and thus make better dispatching decisions. In the systematic evaluation, our segment-aware scheduler consistently shows a significant performance gain on top of the order-of-magnitude speedup of PDES, when compared with the previous scheduling policies.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132510209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748254
Johannes Schreiner, Rainer Findenig, W. Ecker
Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable overhead can be needed to code well-known hardware patterns such as FSMs. Finally, the simulation algorithm prevents efficient simulation (e.g. two-state or cycle-based simulation) as well as advanced model analysis (e.g. X-propagation) or fosters an execution that is not in sync with the language definition. Therefore, we developed a design centric modeling approach that allows a clear specification of the design intent and provides freedom for various target HDLs and modeling styles. Since our approach is specified without underlying simulation semantics, we provide a formal definition considering only certain points in simulation traces, thus enabling various ways for simulation. To avoid syntactic sugar, we selected a metamodeling based approach, which we use as part of a modeldriven generation-focused design approach.
{"title":"Design centric modeling of digital hardware","authors":"Johannes Schreiner, Rainer Findenig, W. Ecker","doi":"10.1109/HLDVT.2016.7748254","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748254","url":null,"abstract":"Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable overhead can be needed to code well-known hardware patterns such as FSMs. Finally, the simulation algorithm prevents efficient simulation (e.g. two-state or cycle-based simulation) as well as advanced model analysis (e.g. X-propagation) or fosters an execution that is not in sync with the language definition. Therefore, we developed a design centric modeling approach that allows a clear specification of the design intent and provides freedom for various target HDLs and modeling styles. Since our approach is specified without underlying simulation semantics, we provide a formal definition considering only certain points in simulation traces, thus enabling various ways for simulation. To avoid syntactic sugar, we selected a metamodeling based approach, which we use as part of a modeldriven generation-focused design approach.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123977995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748263
Qinhao Wang, Yusuke Kimura, M. Fujita
In this paper we discuss techniques by which system level designs in C can be automatically modified or refined to be equivalent to given implementation designs in RTL/netlists, assuming that the numbers of statements in C to be changed are small, e,g., one to several statements. This can correspond to the cases when RTL/gate-level ECO (Engineering Change Order) happens, as under ECO usually small portions of designs or small functionalities are changed. In the proposed method, templates are generated from the original C descriptions by replacing a set of statements with parameterized and programmable statements having symbolic variables that represent program variables, constants, operators and others. Then the problem to refine templates so that the resulting C descriptions become equivalent to the implementation designs is formulated as a QBF (Quantified Boolean Formula) problem. The QBF problem is solved by repeatedly applying SAT solvers in incremental ways without any formal analysis on the implementation designs. Implementation designs are just simulated by a number of times. This process also generates a set of test patterns by which the equivalence between the C descriptions with refined templates and the implementations can be 100% guaranteed as long as the templates can capture the behaviors of the implementation designs. We show preliminary experimental results which show usefulness of the proposed approach.
{"title":"Automatically adjusting system level designs after RTL/gate-level ECO","authors":"Qinhao Wang, Yusuke Kimura, M. Fujita","doi":"10.1109/HLDVT.2016.7748263","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748263","url":null,"abstract":"In this paper we discuss techniques by which system level designs in C can be automatically modified or refined to be equivalent to given implementation designs in RTL/netlists, assuming that the numbers of statements in C to be changed are small, e,g., one to several statements. This can correspond to the cases when RTL/gate-level ECO (Engineering Change Order) happens, as under ECO usually small portions of designs or small functionalities are changed. In the proposed method, templates are generated from the original C descriptions by replacing a set of statements with parameterized and programmable statements having symbolic variables that represent program variables, constants, operators and others. Then the problem to refine templates so that the resulting C descriptions become equivalent to the implementation designs is formulated as a QBF (Quantified Boolean Formula) problem. The QBF problem is solved by repeatedly applying SAT solvers in incremental ways without any formal analysis on the implementation designs. Implementation designs are just simulated by a number of times. This process also generates a set of test patterns by which the equivalence between the C descriptions with refined templates and the implementations can be 100% guaranteed as long as the templates can capture the behaviors of the implementation designs. We show preliminary experimental results which show usefulness of the proposed approach.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116968118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748250
Xian Li, K. Schneider
Property directed reachability (PDR) has been introduced as a very efficient verification method for synchronous hardware circuits which is based on induction rather than fixpoint computation. The method incrementally refines a sequence of clause sets that over-approximate the states that are reachable in finitely many steps. Even being valid, safety properties may not be provable by induction due to so-called counterexamples to induction (CTIs) that result from the over-approximation of the reachable states. Crucial steps of the PDR method therefore consist of (1) deciding about the reachability of states derived from counterexamples, and (2) generalizing them to clauses that cover as many unreachable states as possible that are then excluded from consideration by adding the generated clause to the reachable state approximation sequence. In this paper, we describe a refinement of the PDR method for synchronous programs that makes effective use of the distinction between the control- and dataflow of synchronous programs. If a CTI candidate is found, we reduce it to its control-flow part and check whether the obtained control-flow states are unreachable in the corresponding extended finite state machine of the program. If so, we can immediately exclude all these states by adding the negation of the control-flow part as a new clause to the current reachable state approximations; otherwise, the usual steps of the PDR method are applied. This additional step in the PDR method is not expensive, and can significantly increase the performance of PDR.
{"title":"Control-flow guided clause generation for property directed reachability","authors":"Xian Li, K. Schneider","doi":"10.1109/HLDVT.2016.7748250","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748250","url":null,"abstract":"Property directed reachability (PDR) has been introduced as a very efficient verification method for synchronous hardware circuits which is based on induction rather than fixpoint computation. The method incrementally refines a sequence of clause sets that over-approximate the states that are reachable in finitely many steps. Even being valid, safety properties may not be provable by induction due to so-called counterexamples to induction (CTIs) that result from the over-approximation of the reachable states. Crucial steps of the PDR method therefore consist of (1) deciding about the reachability of states derived from counterexamples, and (2) generalizing them to clauses that cover as many unreachable states as possible that are then excluded from consideration by adding the generated clause to the reachable state approximation sequence. In this paper, we describe a refinement of the PDR method for synchronous programs that makes effective use of the distinction between the control- and dataflow of synchronous programs. If a CTI candidate is found, we reduce it to its control-flow part and check whether the obtained control-flow states are unreachable in the corresponding extended finite state machine of the program. If so, we can immediately exclude all these states by adding the negation of the control-flow part as a new clause to the current reachable state approximations; otherwise, the usual steps of the PDR method are applied. This additional step in the PDR method is not expensive, and can significantly increase the performance of PDR.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115096170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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