{"title":"面向JPEG2000的EBCOT第二层编码器的VLSI架构","authors":"Leibo Liu, Zhihua Wang, Ning Chen, Li Zhang","doi":"10.1109/ICASIC.2005.1611290","DOIUrl":null,"url":null,"abstract":"This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) Tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18 /spl mu/m 1P6M CMOS technology.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"VLSI architecture of EBCOT Tier-2 encoder for JPEG2000\",\"authors\":\"Leibo Liu, Zhihua Wang, Ning Chen, Li Zhang\",\"doi\":\"10.1109/ICASIC.2005.1611290\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) Tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18 /spl mu/m 1P6M CMOS technology.\",\"PeriodicalId\":436123,\"journal\":{\"name\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611290\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611290","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VLSI architecture of EBCOT Tier-2 encoder for JPEG2000
This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) Tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18 /spl mu/m 1P6M CMOS technology.
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