并行快速傅立叶变换的VLSI实现

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC Pub Date : 1994-02-28 DOI:10.1109/EDTC.1994.326869

A. Vacher, M. Benkhebbab, A. Guyot, T. Rousseau, A. Skaf

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引用次数: 12

摘要

本文设计了一种采用在线最高有效位优先算法进行傅里叶变换的VLSI电路。首先回顾了管道快速傅里叶变换的原理，并介绍了一种折叠管道。然后利用在线作业者和作业者合并规则，设计了一种经济有效的蝶形作业者。最后描述了一个具有8个蝴蝶的电路，并与其他实现进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A VLSI implementation of parallel fast Fourier transform

This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.<>

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Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

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