{"title":"容错FFT处理器的分时模块化冗余","authors":"V. Piuri, E. Swartzlander","doi":"10.1109/DFTVS.1999.802893","DOIUrl":null,"url":null,"abstract":"This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Time-shared modular redundancy for fault-tolerant FFT processors\",\"authors\":\"V. Piuri, E. Swartzlander\",\"doi\":\"10.1109/DFTVS.1999.802893\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated.\",\"PeriodicalId\":448322,\"journal\":{\"name\":\"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1999.802893\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1999.802893","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Time-shared modular redundancy for fault-tolerant FFT processors
This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated.
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