一个20ns 64K NMOS内存

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156718

S. Schuster, B. Chappell, V. DiLionardo, P. Britton

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引用次数: 5

摘要

将介绍具有20ns访问时间和30ns周期时间的32.6mm24K×16 NMOS SRAM。SRAM采用4晶体管动态刷新存储单元，具有1.7μm的特征和单级多晶硅。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 20ns 64K NMOS RAM

A 32.6mm24K×16 NMOS SRAM having a 20ns access time and 30ns cycle time will be covered. The SRAM utilizes a 4 transistor dynamic refresh memory cell with 1.7μm features and single level polycide.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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