使用SuperFlash®memBrain™技术进行内存计算

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830145

Nhan Do, H. Tran, M. Reiten

{"title":"使用SuperFlash®memBrain™技术进行内存计算","authors":"Nhan Do, H. Tran, M. Reiten","doi":"10.1109/vlsitechnologyandcir46769.2022.9830145","DOIUrl":null,"url":null,"abstract":"The concept and experimental result of using SuperFlash® based neuromorphic memory to solve the data communication bottlenecks in neural network edge devices are discussed. The implementation of a 2Mb memory array as an analog vector matrix multiplier (VMM) in a 28 nm SuperFlash® eFlash (ESF3-28 nm) process together with design concepts, weight tuning technique, performance factors, and reliability, are also presented in detail.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Computing-in-Memory with SuperFlash® memBrain™ Technology\",\"authors\":\"Nhan Do, H. Tran, M. Reiten\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830145\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The concept and experimental result of using SuperFlash® based neuromorphic memory to solve the data communication bottlenecks in neural network edge devices are discussed. The implementation of a 2Mb memory array as an analog vector matrix multiplier (VMM) in a 28 nm SuperFlash® eFlash (ESF3-28 nm) process together with design concepts, weight tuning technique, performance factors, and reliability, are also presented in detail.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

讨论了利用基于SuperFlash®的神经形态存储器解决神经网络边缘设备数据通信瓶颈的概念和实验结果。在28纳米SuperFlash®eFlash (ESF3-28纳米)工艺中实现2Mb存储器阵列作为模拟向量矩阵乘法器(VMM)，并详细介绍了设计概念、权重调谐技术、性能因素和可靠性。

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Computing-in-Memory with SuperFlash® memBrain™ Technology

The concept and experimental result of using SuperFlash® based neuromorphic memory to solve the data communication bottlenecks in neural network edge devices are discussed. The implementation of a 2Mb memory array as an analog vector matrix multiplier (VMM) in a 28 nm SuperFlash® eFlash (ESF3-28 nm) process together with design concepts, weight tuning technique, performance factors, and reliability, are also presented in detail.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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