K. Seidel, D. Lehninger, R. Hoffmann, T. Ali, M. Lederer, Ricardo Revello, K. Mertens, K. Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, A. Heinig, T. Kämpfe, H. Mähne, K. Bernert, S. Thiem
{"title":"存储器阵列展示了完全集成的1T-1C ffet概念，并在互连层中分离了铁电MFM器件","authors":"K. Seidel, D. Lehninger, R. Hoffmann, T. Ali, M. Lederer, Ricardo Revello, K. Mertens, K. Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, A. Heinig, T. Kämpfe, H. Mähne, K. Bernert, S. Thiem","doi":"10.1109/vlsitechnologyandcir46769.2022.9830141","DOIUrl":null,"url":null,"abstract":"In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer\",\"authors\":\"K. Seidel, D. Lehninger, R. Hoffmann, T. Ali, M. Lederer, Ricardo Revello, K. Mertens, K. Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, A. Heinig, T. Kämpfe, H. Mähne, K. Bernert, S. Thiem\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830141\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830141\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer
In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.
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