{"title":"16nm栅极CMOS器件中Si/高氧化硅界面陷阱和随机掺杂引起的电特性波动的三维模拟","authors":"Hui-Wen Cheng, Y. Chiu, Yiming Li","doi":"10.1109/DRC.2011.5994435","DOIUrl":null,"url":null,"abstract":"The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"3D simulation of electrical characteristic fluctuation induced by interface traps at Si/high-к oxide interface and random dopants in 16-nm-Gate CMOS devices\",\"authors\":\"Hui-Wen Cheng, Y. Chiu, Yiming Li\",\"doi\":\"10.1109/DRC.2011.5994435\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.\",\"PeriodicalId\":107059,\"journal\":{\"name\":\"69th Device Research Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"69th Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2011.5994435\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"69th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2011.5994435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
3D simulation of electrical characteristic fluctuation induced by interface traps at Si/high-к oxide interface and random dopants in 16-nm-Gate CMOS devices
The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.