H.-C. Oh, H.-G. Kim, H.-S. Jung, J.-W. Lee, B. Kim, J. Jung, B.-G. Min, J.-Y. Lim, H. Lee, Kyeonghwan Kwon
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The ADC's EISC microprocessor family has been developed to address the need for reduction in the amount of memory access of today's embedded applications. In this paper, we introduce the microarchitecture of the AE32000 processor, a 32-bit member of the ADC's EISC family. Specifically, we discuss the pipelining scheme and LERI-instruction folding, and we present the performance of our current implementation. We also introduce a system implementation utilizing the AE32000 processor.
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