可扩展的0.35V至1.2V SRAM位单元设计，从65nm CMOS到28nm FDSOI

2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI:10.1109/ESSCIRC.2013.6649108

F. Abouzeid, A. Bienfait, K. Akyel, S. Clerc, L. Ciampolini, P. Roche

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引用次数: 8

摘要

我们提出了一种可扩展的超宽电压范围(UWVR) SRAM位单元阵列的设计和表征方法，目标是最小电压预测，高产量和Si-CAD相关性在5%以内。首先在65nm CMOS上进行了实验验证，然后在28nm FDSOI上进行了验证。在标称电压下测量高速时，在1.2V至0.35V范围内实现了超过10倍的能量增益。

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Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10× energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.

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2013 Proceedings of the ESSCIRC (ESSCIRC)

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