{"title":"拉伸封盖层对FinFET通道三维应力分布的影响","authors":"K. Shin, T. Lauderdale, T. King","doi":"10.1109/DRC.2005.1553120","DOIUrl":null,"url":null,"abstract":"Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Effect of tensile capping layer on 3-D stress profiles in FinFET channels\",\"authors\":\"K. Shin, T. Lauderdale, T. King\",\"doi\":\"10.1109/DRC.2005.1553120\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator\",\"PeriodicalId\":306160,\"journal\":{\"name\":\"63rd Device Research Conference Digest, 2005. DRC '05.\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"63rd Device Research Conference Digest, 2005. DRC '05.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2005.1553120\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. DRC '05.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2005.1553120","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of tensile capping layer on 3-D stress profiles in FinFET channels
Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator
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