V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino
{"title":"地平面对UTBB SOI nMOSFET模拟参数的影响","authors":"V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino","doi":"10.1109/SBMICRO.2015.7298114","DOIUrl":null,"url":null,"abstract":"This paper presents an analysis of the Ground Plane (GP) influence on analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices based on experimental data and simulations results. The presence of a GP improves the transconductance in the saturation region due to the strong coupling between front and back gates. However, the GP worsens the output conductance due to the higher drain electrical field penetration observed by simulation. As a result, the devices without ground plane present better results in intrinsic voltage gain, Early Voltage and Drain Induced Barrier Lowering.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Ground Plane influence on UTBB SOI nMOSFET analog parameters\",\"authors\":\"V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino\",\"doi\":\"10.1109/SBMICRO.2015.7298114\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an analysis of the Ground Plane (GP) influence on analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices based on experimental data and simulations results. The presence of a GP improves the transconductance in the saturation region due to the strong coupling between front and back gates. However, the GP worsens the output conductance due to the higher drain electrical field penetration observed by simulation. As a result, the devices without ground plane present better results in intrinsic voltage gain, Early Voltage and Drain Induced Barrier Lowering.\",\"PeriodicalId\":342493,\"journal\":{\"name\":\"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"volume\":\"117 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBMICRO.2015.7298114\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMICRO.2015.7298114","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ground Plane influence on UTBB SOI nMOSFET analog parameters
This paper presents an analysis of the Ground Plane (GP) influence on analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices based on experimental data and simulations results. The presence of a GP improves the transconductance in the saturation region due to the strong coupling between front and back gates. However, the GP worsens the output conductance due to the higher drain electrical field penetration observed by simulation. As a result, the devices without ground plane present better results in intrinsic voltage gain, Early Voltage and Drain Induced Barrier Lowering.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
