{"title":"一种用于模数转换器的嵌入式内置自检方法","authors":"Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang","doi":"10.1109/ATS.2002.1181722","DOIUrl":null,"url":null,"abstract":"In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An embedded built-in-self-test approach for analog-to-digital converters\",\"authors\":\"Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang\",\"doi\":\"10.1109/ATS.2002.1181722\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.\",\"PeriodicalId\":199542,\"journal\":{\"name\":\"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2002.1181722\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2002.1181722","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An embedded built-in-self-test approach for analog-to-digital converters
In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.
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