Performance Evaluation of One Dimensional Systolic Array for FFT Processor

A new approach for the systolic implementation of FFT algorithms is presented, the proposed approach is based on the fundamental principle of 1-dimensional DFT can be decomposed efficiently with less number of twiddle values and also the computation burden involved with multipliers is reduced considerably, the FFT can be computed efficiently with 1-D systolic array, the essence of 1D systolic array is to have efficient computation with less twiddles, the proposed systolic array does not require any preloading of input data and it produces output data at boundary PES. No networks for intermediate spectrum transposition between constituent I-dimensional transforms are required: therefore the entire processing is fully pipelined. This approach also has significant advantages over existing architectures in reduced complexity with Wallace tree adder and Booth multiplier