{"title":"带约束的单元格编译","authors":"C. Lursinsap, D. Gajski","doi":"10.1109/DAC.1984.1585781","DOIUrl":null,"url":null,"abstract":"This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"412 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Cell Compilation with Constraints\",\"authors\":\"C. Lursinsap, D. Gajski\",\"doi\":\"10.1109/DAC.1984.1585781\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.\",\"PeriodicalId\":188431,\"journal\":{\"name\":\"21st Design Automation Conference Proceedings\",\"volume\":\"412 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1984-06-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"21st Design Automation Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1984.1585781\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st Design Automation Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1984.1585781","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.
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