Low-Latency FPGA Design and Implementation of Hermitian Matrix Inversion Based on Partitioned Systolic Array for Massive MIMO

Large-scale matrix inversion is widely used in massive Multiple Input Multiple Output (MIMO) beamforming systems, but matrix inversion is very complicated in hardware implementation. In this paper, Hermitian matrix decomposition method based on partitioned systolic array is proposed, and the computing structure of the algorithm is improved flexibly by utilizing the partitioned characteristics of large-scale matrix. We compare our method with existing FPGA-based technologies on Xilinx ZCU102 FPGA. The results of the experiment show that our method has better performance than existing techniques in resource utilization, device delay and maximum working frequency when the size of Hermitian matrix is 32 × 32, which is a typical size for MIMO applications.