III–V MOS technology: From planar to 3D and 4D

Recently, III-V MOSFETs with high drain currents (Ids>1mA/μm) and high transconductances (gm>1mS/μm) have been achieved at sub-micron channel lengths (Lch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of deep sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V MOS technology developed very recently. We will also report some of new progress by demonstration of 20-80 nm channel length III-V gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63 mV/dec. The total drain current per pitch can be further enhanced by introducing 4D structures.