Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture

This article proposes a spatio-temporal scheduling algorithm for a three-dimensional integrated circuits (3D ICs) defined by stacking an homogeneous embedded Field-Programmable Gate Array (eFPGA) above an homogenous Chip MultiProcessor (CMP) layer over through-silicon vias (TSVs) connection. Our proposal, based on Proportionate-fair (Pfair) algorithm, computes the spatio-temporal scheduling of hardware tasks on the reconfigurable resources by taking into account the communication between tasks and then places the associated software tasks on the multiprocessors layer. Compared to the “equivalent” solutions produced by the recursive Branch and Bound (BB) algorithm, our proposal shows up to 14,5% communication cost reduction.