基于FinFET技术的随机计算电路Vdd缩放极限研究

2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI:10.23919/SNW.2017.8242341

Xiaobo Jiang, Runsheng Wang, Shaofeng Guo, Ru Huang

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引用次数: 1

摘要

基于晶圆厂级16/14nm FinFET技术，考虑固有、静态和瞬态变化，研究了随机计算中电源电压(Vdd)的缩放极限。测试了电路功能、EDP和算术误差，表明瞬态变化引起的算术偏差是主要因素。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Investigation on the Vdd scaling limit of stochastic computing circuits based on FinFET technology

The scaling limits of supply voltage (Vdd) in stochastic computing are investigated based on foundry-level 16/14nm FinFET technology, considering inherent, static and transient variations. Circuit functionality, EDP, arithmetic error are examined, indicating that transient variation induced arithmetic bias is the dominating factor.

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2017 Silicon Nanoelectronics Workshop (SNW)

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