{"title":"面向高层次设计的仿真与建模","authors":"J. Barby, C. Ryan","doi":"10.1109/ASIC.1998.722999","DOIUrl":null,"url":null,"abstract":"With the drive to ULSI design, the concept of design of the complete chip being done within a single design team is becoming rare. These large designs include large pieces of intellectual property (IP) from previous designs (design reuse) or imported from another company or design team (design core). To compound this, ULSI power budget targets are more difficult to meet than in the past when design complexity was less. In this session varying approaches to address these issues are discussed.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Simulation And Modeling For High Level Design\",\"authors\":\"J. Barby, C. Ryan\",\"doi\":\"10.1109/ASIC.1998.722999\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the drive to ULSI design, the concept of design of the complete chip being done within a single design team is becoming rare. These large designs include large pieces of intellectual property (IP) from previous designs (design reuse) or imported from another company or design team (design core). To compound this, ULSI power budget targets are more difficult to meet than in the past when design complexity was less. In this session varying approaches to address these issues are discussed.\",\"PeriodicalId\":104431,\"journal\":{\"name\":\"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1998.722999\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
With the drive to ULSI design, the concept of design of the complete chip being done within a single design team is becoming rare. These large designs include large pieces of intellectual property (IP) from previous designs (design reuse) or imported from another company or design team (design core). To compound this, ULSI power budget targets are more difficult to meet than in the past when design complexity was less. In this session varying approaches to address these issues are discussed.