X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph
{"title":"SOI CMOS中8500V防静电SP10T开关并行设计分析","authors":"X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph","doi":"10.1109/S3S.2013.6716560","DOIUrl":null,"url":null,"abstract":"SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"540 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Concurrent design analysis of A 8500V ESD-protected SP10T switch in SOI CMOS\",\"authors\":\"X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph\",\"doi\":\"10.1109/S3S.2013.6716560\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].\",\"PeriodicalId\":219932,\"journal\":{\"name\":\"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"540 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2013.6716560\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2013.6716560","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Concurrent design analysis of A 8500V ESD-protected SP10T switch in SOI CMOS
SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].
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