用于纳米技术应用的高效ALU结构拓扑

Anum Khan, Subodh Wairya
{"title":"用于纳米技术应用的高效ALU结构拓扑","authors":"Anum Khan, Subodh Wairya","doi":"10.1109/SPIN52536.2021.9566043","DOIUrl":null,"url":null,"abstract":"In this paper, a highly efficient ALU architecture is designed using Carbon Nanotube Field effect Transistor(CNTFET) and conventional MOSFET. High performing Multiplexer (Mux) based full adder is used for this purpose. First the performance of Transmission gate(TG) based Multiplexer and Pass transistor logic(PTL) based multiplexer are compared. Extensive performance analysis of several low transistor count hybrid adders has been done based on their power, delay, and PDP and thereby establishing Mux based Full Adder(FA) as the more efficient adder topology. The 4 bit ALU is implemented using the Mux based adder and its performance is compared with its CNTFET implementation. All the simulations are done using Cadence Virtuoso by 45nm technology for MOSFET and 10nm technology for CNTFET at 27°C for a supply voltage range of 0.6V to 1.2V. The CNTFET based circuits were designed to appraise their compatibility with conventional transistors and show considerable performance improvement.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Efficient ALU Architecture Topology for Nanotechnology Applications\",\"authors\":\"Anum Khan, Subodh Wairya\",\"doi\":\"10.1109/SPIN52536.2021.9566043\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a highly efficient ALU architecture is designed using Carbon Nanotube Field effect Transistor(CNTFET) and conventional MOSFET. High performing Multiplexer (Mux) based full adder is used for this purpose. First the performance of Transmission gate(TG) based Multiplexer and Pass transistor logic(PTL) based multiplexer are compared. Extensive performance analysis of several low transistor count hybrid adders has been done based on their power, delay, and PDP and thereby establishing Mux based Full Adder(FA) as the more efficient adder topology. The 4 bit ALU is implemented using the Mux based adder and its performance is compared with its CNTFET implementation. All the simulations are done using Cadence Virtuoso by 45nm technology for MOSFET and 10nm technology for CNTFET at 27°C for a supply voltage range of 0.6V to 1.2V. The CNTFET based circuits were designed to appraise their compatibility with conventional transistors and show considerable performance improvement.\",\"PeriodicalId\":343177,\"journal\":{\"name\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN52536.2021.9566043\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN52536.2021.9566043","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文采用碳纳米管场效应晶体管(CNTFET)和传统的MOSFET设计了一种高效的ALU结构。基于高性能多路复用器(Mux)的全加法器用于此目的。首先比较了基于传输门(TG)的多路复用器和基于通管逻辑(PTL)的多路复用器的性能。基于功率、延迟和PDP对几种低晶体管计数混合加法器进行了广泛的性能分析,从而建立了基于Mux的全加法器(FA)作为更有效的加法器拓扑。采用基于Mux的加法器实现了4位ALU,并将其性能与CNTFET实现进行了比较。所有仿真均使用Cadence Virtuoso在27°C、0.6V至1.2V的电源电压范围下,采用45nm技术对MOSFET和10nm技术对cnfet进行。设计了基于CNTFET的电路,以评估其与传统晶体管的兼容性,并显示出相当大的性能改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
An Efficient ALU Architecture Topology for Nanotechnology Applications
In this paper, a highly efficient ALU architecture is designed using Carbon Nanotube Field effect Transistor(CNTFET) and conventional MOSFET. High performing Multiplexer (Mux) based full adder is used for this purpose. First the performance of Transmission gate(TG) based Multiplexer and Pass transistor logic(PTL) based multiplexer are compared. Extensive performance analysis of several low transistor count hybrid adders has been done based on their power, delay, and PDP and thereby establishing Mux based Full Adder(FA) as the more efficient adder topology. The 4 bit ALU is implemented using the Mux based adder and its performance is compared with its CNTFET implementation. All the simulations are done using Cadence Virtuoso by 45nm technology for MOSFET and 10nm technology for CNTFET at 27°C for a supply voltage range of 0.6V to 1.2V. The CNTFET based circuits were designed to appraise their compatibility with conventional transistors and show considerable performance improvement.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Temperature Compensation Circuit for ISFET based pH Sensor Knowledge Adaptation for Cross-Domain Opinion Mining Voltage Profile Enhancement of a 33 Bus System Integrated with Renewable Energy Sources and Electric Vehicle Power Quality Enhancement of Cascaded H Bridge 5 Level and 7 Level Inverters PIC simulation study of Beam Tunnel for W- Band high power Gyrotron
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1