B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog
{"title":"Pr/sub 2/O/sub 3/在Si上的分子束外延","authors":"B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog","doi":"10.1109/DRC.2005.1553068","DOIUrl":null,"url":null,"abstract":"Crystalline high-k oxides epitaxially grown on Si which allow further reduction of equivalent oxide thickness (EOT), are potential candidates for gate dielectrics in the 32 nm CMOS technology mode requiring EOT < 1 nm beyond 2013. Epitaxial growth of perovskite-type oxides on Si for gate dielectrics was demonstrated and high transistor mobility was achieved (McKee et al., 2001). Here we report on molecular beam epitaxy (MBE) of binary praseodymium oxide Pr2O3 on Si (001) which according to thermodynamics should be stable against silicon. Two different phases of Pr2O3exist, a cubic phase with a lattice constant of 11.152 Aring, and a hexagonal phase with a=3.8577 Aring and c=6.012 Aring (Burnham and Eyring, 1968 and Adachi and Imanaka, 1998). The misfit between a/2 of the cubic phase and the Si lattice constant is about 2.7%. The misfit in the (0001) plane of the hexagonal Pr2 O3relative to the (111) plane of Si is only 0.5%. Preliminary results show (Osten et al., 2001) that crystalline Pr2 O3grown on Si(001) is a promising candidate for scaled gate insulators, displaying sufficiently high-k (k=30) combined with ultra-low leakage current density (10-8 A/cm2 at V g0 = plusmn 1 V for EOT = 1.4 nm) and good reliability. It is crucial to avoid the formation of interlayers at the Pr2O 3/Si interface, as any low-k silicate-like layers represent a low capacity in series which deteriorates the desired capacity effect of the high-k oxide","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Molecular beam epitaxy of Pr/sub 2/O/sub 3/on Si\",\"authors\":\"B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog\",\"doi\":\"10.1109/DRC.2005.1553068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Crystalline high-k oxides epitaxially grown on Si which allow further reduction of equivalent oxide thickness (EOT), are potential candidates for gate dielectrics in the 32 nm CMOS technology mode requiring EOT < 1 nm beyond 2013. Epitaxial growth of perovskite-type oxides on Si for gate dielectrics was demonstrated and high transistor mobility was achieved (McKee et al., 2001). Here we report on molecular beam epitaxy (MBE) of binary praseodymium oxide Pr2O3 on Si (001) which according to thermodynamics should be stable against silicon. Two different phases of Pr2O3exist, a cubic phase with a lattice constant of 11.152 Aring, and a hexagonal phase with a=3.8577 Aring and c=6.012 Aring (Burnham and Eyring, 1968 and Adachi and Imanaka, 1998). The misfit between a/2 of the cubic phase and the Si lattice constant is about 2.7%. The misfit in the (0001) plane of the hexagonal Pr2 O3relative to the (111) plane of Si is only 0.5%. Preliminary results show (Osten et al., 2001) that crystalline Pr2 O3grown on Si(001) is a promising candidate for scaled gate insulators, displaying sufficiently high-k (k=30) combined with ultra-low leakage current density (10-8 A/cm2 at V g0 = plusmn 1 V for EOT = 1.4 nm) and good reliability. It is crucial to avoid the formation of interlayers at the Pr2O 3/Si interface, as any low-k silicate-like layers represent a low capacity in series which deteriorates the desired capacity effect of the high-k oxide\",\"PeriodicalId\":306160,\"journal\":{\"name\":\"63rd Device Research Conference Digest, 2005. DRC '05.\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"63rd Device Research Conference Digest, 2005. DRC '05.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2005.1553068\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. DRC '05.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2005.1553068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
在Si上外延生长的晶体高k氧化物允许进一步降低等效氧化物厚度(EOT),是2013年以后要求EOT < 1nm的32nm CMOS技术模式中栅极电介质的潜在候选者。证明了钙钛矿型氧化物在硅上的外延生长,并实现了高晶体管迁移率(McKee et al., 2001)。本文报道了二元氧化镨Pr2O3在Si(001)上的分子束外延(MBE),根据热力学,它对硅是稳定的。pr2o3存在两种不同的相,晶格常数为11.152 Aring的立方相和晶格常数为3.8577 Aring和c=6.012 Aring的六方相(Burnham and Eyring, 1968; Adachi and Imanaka, 1998)。三次相的a/2与Si晶格常数的误差约为2.7%。六边形pr2o3的(0001)面相对于Si的(111)面误差仅为0.5%。初步结果表明(Osten et al., 2001),在Si(001)上生长的结晶pr2o3是一种很有前途的栅极绝缘体,具有足够高的k (k=30)和超低漏电流密度(10-8 a /cm2,电压g0 = + 1 V, EOT = 1.4 nm)和良好的可靠性。避免在Pr2O /Si界面处形成中间层是至关重要的,因为任何低钾硅酸盐样层都代表低容量串联,从而恶化了高钾氧化物的期望容量效果
Crystalline high-k oxides epitaxially grown on Si which allow further reduction of equivalent oxide thickness (EOT), are potential candidates for gate dielectrics in the 32 nm CMOS technology mode requiring EOT < 1 nm beyond 2013. Epitaxial growth of perovskite-type oxides on Si for gate dielectrics was demonstrated and high transistor mobility was achieved (McKee et al., 2001). Here we report on molecular beam epitaxy (MBE) of binary praseodymium oxide Pr2O3 on Si (001) which according to thermodynamics should be stable against silicon. Two different phases of Pr2O3exist, a cubic phase with a lattice constant of 11.152 Aring, and a hexagonal phase with a=3.8577 Aring and c=6.012 Aring (Burnham and Eyring, 1968 and Adachi and Imanaka, 1998). The misfit between a/2 of the cubic phase and the Si lattice constant is about 2.7%. The misfit in the (0001) plane of the hexagonal Pr2 O3relative to the (111) plane of Si is only 0.5%. Preliminary results show (Osten et al., 2001) that crystalline Pr2 O3grown on Si(001) is a promising candidate for scaled gate insulators, displaying sufficiently high-k (k=30) combined with ultra-low leakage current density (10-8 A/cm2 at V g0 = plusmn 1 V for EOT = 1.4 nm) and good reliability. It is crucial to avoid the formation of interlayers at the Pr2O 3/Si interface, as any low-k silicate-like layers represent a low capacity in series which deteriorates the desired capacity effect of the high-k oxide