测试带有携带逻辑模块的Xilinx XC4000可配置逻辑块

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2001-10-24 DOI:10.1109/DFTVS.2001.966774

Xiaoling Sun, Jian Xu, P. Trouborst

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引用次数: 8

摘要

针对Xilinx XC4000现场可编程门阵列(fpga)的可配置逻辑块(clb)，提出了一种新的内置自检(BIST)方案。本文首次纳入了CLB内专用进位逻辑模块(CLM)的测试。给出了至少8个CLB测试配置。集中式BIST架构支持对CLM和整个CLB进行单卡故障测试。该方案还能够以最大诊断分辨率定位任何故障clb，两个相邻的clb。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Testing Xilinx XC4000 configurable logic blocks with carry logic-modules

This paper presents a novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time. A minimum of eight CLB test configurations is given. A centralized BIST architecture supports the single stuck-at fault test of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs.

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Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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