L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell
{"title":"一种CMOS宽带调谐器IC","authors":"L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell","doi":"10.1109/ISSCC.2002.993101","DOIUrl":null,"url":null,"abstract":"A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"47","resultStr":"{\"title\":\"A CMOS broadband tuner IC\",\"authors\":\"L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell\",\"doi\":\"10.1109/ISSCC.2002.993101\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"242 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"47\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.993101\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.993101","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.