F. Yang, J. O'Neill, P. Larsson, D. Inglis, J. Othmer
{"title":"一个1.5 V 86 mW/ch 8通道622-3125 Mb/s/ch CMOS SerDes macrocell,具有可选的多路/失路比","authors":"F. Yang, J. O'Neill, P. Larsson, D. Inglis, J. Othmer","doi":"10.1109/ISSCC.2002.992103","DOIUrl":null,"url":null,"abstract":"An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"A 1.5 V 86 mW/ch 8-channel 622-3125 Mb/s/ch CMOS SerDes macrocell with selectable mux/demux ratio\",\"authors\":\"F. Yang, J. O'Neill, P. Larsson, D. Inglis, J. Othmer\",\"doi\":\"10.1109/ISSCC.2002.992103\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"152 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992103\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992103","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.5 V 86 mW/ch 8-channel 622-3125 Mb/s/ch CMOS SerDes macrocell with selectable mux/demux ratio
An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.