{"title":"采用RTA和等离子体加氢技术的高性能多晶硅TFT，适用于16mbit及以上的高稳定sram","authors":"F. Hayashi, M. Kitakata","doi":"10.1109/VLSIT.1992.200634","DOIUrl":null,"url":null,"abstract":"A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond\",\"authors\":\"F. Hayashi, M. Kitakata\",\"doi\":\"10.1109/VLSIT.1992.200634\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200634\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200634","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond
A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<>
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