{"title":"CPU产生的二元和三元负载的电力输送评估","authors":"W. Lambert, R. Ayyanar","doi":"10.1109/EPEP.2007.4387108","DOIUrl":null,"url":null,"abstract":"CPU generated loads useful for analysis and characterization of microprocessor power delivery networks are described along with potential applications. The loads are generated by a functional microprocessor operating in PLL BYPASS mode.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"333 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"CPU Generated Binary and Ternary Loads for Power Delivery Assessment\",\"authors\":\"W. Lambert, R. Ayyanar\",\"doi\":\"10.1109/EPEP.2007.4387108\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CPU generated loads useful for analysis and characterization of microprocessor power delivery networks are described along with potential applications. The loads are generated by a functional microprocessor operating in PLL BYPASS mode.\",\"PeriodicalId\":402571,\"journal\":{\"name\":\"2007 IEEE Electrical Performance of Electronic Packaging\",\"volume\":\"333 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Electrical Performance of Electronic Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2007.4387108\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2007.4387108","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CPU Generated Binary and Ternary Loads for Power Delivery Assessment
CPU generated loads useful for analysis and characterization of microprocessor power delivery networks are described along with potential applications. The loads are generated by a functional microprocessor operating in PLL BYPASS mode.
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