采用非线性双插值技术，在0.13 /spl mu/m数字CMOS工艺中实现了嵌入式0.8 V/480 /spl mu/W 6b/22 MHz闪存ADC

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992235

J. Lin, B. Haroun

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引用次数: 22

摘要

为实现高数据速率无线通信，在0.13 /spl mu/m的数字CMOS中，制作了一个0.8 V 480 /spl mu/W 6b 22 MSample/s的闪存插值ADC。该电路采用非线性双插值技术实现了33 dB的SNDR和47 dB的SFDR。

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An embedded 0.8 V/480 /spl mu/W 6b/22 MHz flash ADC in 0.13 /spl mu/m digital CMOS process using nonlinear double-interpolation technique

For high-data-rate wireless communication, a 0.8 V 480 /spl mu/W 6b 22 MSample/s flash-interpolation ADC is fabricated in 0.13 /spl mu/m digital CMOS. The circuit achieves 33 dB SNDR and 47 dB SFDR using a nonlinear double-interpolation technique.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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