四阶LP ΣΔ调制器的行为建模——迈向混合方案的设计

J. G. García-Sánchez, D. Calderón-Preciado, F. Sandoval-Ibarra, J. M. Rosa
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引用次数: 5

摘要

混合ΣΔ调制器具有利用CT和DT架构能力的特性,因此在级联方法中非常有效。在本文中,我们展示了SIMSIDES中ΣΔ调制器的行为模拟。一组基于SC ΣΔ调制器整体性能分析模型的实验被用于将设计考虑转化为一组值,从而使晶体管级的设计能够根据所提出的架构的期望性能来建立。这种设计方法并不是最准确的,但它可以让设计师对所设计的系统有一个大致的理解,这是一种最高抽象层次的理解。所研究的系统是级联四阶混合ΣΔ调制器,其中第二级是二阶低通(LP) DT ΣΔ调制器。DT调制器的理想行为性能被用作展示必须如何考虑非理想性的载体,以及如何将设计考虑转化为晶体管级设计构建块的一组物理值。
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Behavioral modelling of a 4th order LP ΣΔ modulator-towards the design of a hybrid proposal
Hybrid ΣΔ modulator has the property of take advantage of the capabilities of CT and DT architectures and is thus very effective in the cascade approach. In this paper, we show the behavioral simulation of ΣΔ modulators in SIMSIDES. A set of experiments based on models for analyzing the overall performance of SC ΣΔ modulators were used in order to translate design considerations into a set of values such that the design at transistor level be established by the desired performance of the proposed architecture. This design methodology is not the most accurate but it allows the designer to get a general comprehension of the system under design, a comprehension at the highest level of abstraction. The system under study is a cascade 4th order hybrid ΣΔ modulator, from which the second stage is a 2nd order Low-Pass (LP) DT ΣΔ modulator. The ideal behavioral performance of the DT modulator is used as vehicle to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values for designing building blocks at transistor level.
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