{"title":"0.18µm工艺中包络检测器电路的CMOS实现","authors":"P. Fahsyar, N. Soin","doi":"10.1109/SMELEC.2010.5549383","DOIUrl":null,"url":null,"abstract":"This paper presents an envelope detector circuit design for RFID applications implemented in 0.18µm CMOS technology. Towards the design compatibility with standard digital CMOS process, the doubler cell, diode connected PMOS and low transconductance transistor are chosen to place in the rectifier section and to replace the conventional diode as well as the resistor. The proposed envelope detector circuit was simulated with a 150mV – 250mV input signal. With 0.2 modulation index at 900MHz carrier frequency, the power dissipation is found to be 18.8µW at 27°C.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"CMOS implementation of envelope detector circuit in 0.18µm Process\",\"authors\":\"P. Fahsyar, N. Soin\",\"doi\":\"10.1109/SMELEC.2010.5549383\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an envelope detector circuit design for RFID applications implemented in 0.18µm CMOS technology. Towards the design compatibility with standard digital CMOS process, the doubler cell, diode connected PMOS and low transconductance transistor are chosen to place in the rectifier section and to replace the conventional diode as well as the resistor. The proposed envelope detector circuit was simulated with a 150mV – 250mV input signal. With 0.2 modulation index at 900MHz carrier frequency, the power dissipation is found to be 18.8µW at 27°C.\",\"PeriodicalId\":308501,\"journal\":{\"name\":\"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2010.5549383\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2010.5549383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS implementation of envelope detector circuit in 0.18µm Process
This paper presents an envelope detector circuit design for RFID applications implemented in 0.18µm CMOS technology. Towards the design compatibility with standard digital CMOS process, the doubler cell, diode connected PMOS and low transconductance transistor are chosen to place in the rectifier section and to replace the conventional diode as well as the resistor. The proposed envelope detector circuit was simulated with a 150mV – 250mV input signal. With 0.2 modulation index at 900MHz carrier frequency, the power dissipation is found to be 18.8µW at 27°C.
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