事件驱动电路仿真的可变精度器件建模

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC Pub Date : 1994-02-28 DOI:10.1109/EDTC.1994.326819

K. Michaels, A. Strojwas

{"title":"事件驱动电路仿真的可变精度器件建模","authors":"K. Michaels, A. Strojwas","doi":"10.1109/EDTC.1994.326819","DOIUrl":null,"url":null,"abstract":"This paper presents a complete variable accuracy device modeling methodology which varies the error tolerances and device model accuracy during the simulation based upon the dynamic state of operation of the circuit and the circuit topology. The number of device model evaluations required and the average device model evaluation time are minimized.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Variable accuracy device modeling for event-driven circuit simulation\",\"authors\":\"K. Michaels, A. Strojwas\",\"doi\":\"10.1109/EDTC.1994.326819\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a complete variable accuracy device modeling methodology which varies the error tolerances and device model accuracy during the simulation based upon the dynamic state of operation of the circuit and the circuit topology. The number of device model evaluations required and the average device model evaluation time are minimized.<<ETX>>\",\"PeriodicalId\":244297,\"journal\":{\"name\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"volume\":\"75 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1994.326819\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

本文提出了一种完整的变精度器件建模方法，该方法根据电路的动态工作状态和电路拓扑结构，在仿真过程中改变误差容限和器件模型精度。设备模型评估所需的数量和平均设备模型评估时间被最小化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Variable accuracy device modeling for event-driven circuit simulation

This paper presents a complete variable accuracy device modeling methodology which varies the error tolerances and device model accuracy during the simulation based upon the dynamic state of operation of the circuit and the circuit topology. The number of device model evaluations required and the average device model evaluation time are minimized.<>

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Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

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