J. Tinoco, J. Alvarado, A. G. Martinez-Lopez, J. Raskin
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引用次数: 14

摘要

三栅极finfet已被证明有希望进一步推动CMOS技术的缩小,这要归功于它们对所谓的短通道效应的高抗扰性。然而,由于它们的三维结构,它们的模拟特性有很强的退化,这主要是由于大的外在电阻和电容。在本文中,基于测量和三维数值模拟,我们分析了外部栅极电容对finfet射频行为的影响。结果表明,在亚100nm器件中,外源电容大于内源电容。此外,翅片间距的减小以及翅片几何长宽比(高/宽)的增加可以显著改善finfet的射频性能。
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Impact of extrinsic capacitances on FinFETs RF performance
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations we analyze the impact of the extrinsic gate capacitance on the RF behavior of FinFETs. It observes that the extrinsic capacitances are larger than the intrinsic counterparts for sub-100 nm devices. Furthermore, the reduction of the fin spacing as well as the increase of the fin geometrical aspect ratio (height/width) can improve significantly the FinFETs RF behavior.
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