{"title":"栅极环极和三栅极沟道垂直场效应管的寄生电容和性能分析","authors":"Youngsoo Seo, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242298","DOIUrl":null,"url":null,"abstract":"The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Analysis of parasitic capacitance and performance in gate-ail-around and tri-gate channel vertical FET\",\"authors\":\"Youngsoo Seo, Myounggon Kang, Hyungcheol Shin\",\"doi\":\"10.23919/SNW.2017.8242298\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.\",\"PeriodicalId\":424135,\"journal\":{\"name\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2017.8242298\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of parasitic capacitance and performance in gate-ail-around and tri-gate channel vertical FET
The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
