Sabareesh Nikhil Chinta, S. Mittal, P. Debashis, U. Ganguly
{"title":"一种效率提高300倍的FinFET LER VT变异性估计方案","authors":"Sabareesh Nikhil Chinta, S. Mittal, P. Debashis, U. Ganguly","doi":"10.1109/SISPAD.2014.6931617","DOIUrl":null,"url":null,"abstract":"In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (VT) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error <; 10%) with a decrease in computation time of over 300×. The method thus proposed provides a fast and accurate way of estimating σVT from LER specifications of a fin patterning technology.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A FinFET LER VT variability estimation scheme with 300× efficiency improvement\",\"authors\":\"Sabareesh Nikhil Chinta, S. Mittal, P. Debashis, U. Ganguly\",\"doi\":\"10.1109/SISPAD.2014.6931617\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (VT) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error <; 10%) with a decrease in computation time of over 300×. The method thus proposed provides a fast and accurate way of estimating σVT from LER specifications of a fin patterning technology.\",\"PeriodicalId\":101858,\"journal\":{\"name\":\"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2014.6931617\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2014.6931617","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A FinFET LER VT variability estimation scheme with 300× efficiency improvement
In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (VT) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error <; 10%) with a decrease in computation time of over 300×. The method thus proposed provides a fast and accurate way of estimating σVT from LER specifications of a fin patterning technology.
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